This invention pertains to a spacer formation process for non-volatile memory devices. In particular, this invention is directed to a method for performing a two-step spacer deposition and etch resulting in the different appearance of a core and periphery of a non-volatile memory device. Additionally, this invention is related to a non-volatile memory device produced by the above method.
A semiconductor contains at least a core and periphery areas. Generally, memory information storage takes place in the core of a semiconductor. Additionally, storage of electronic charge also commonly occurs in the core. The core includes a plurality of core cells. The core cells are arranged in an ordered array known as a core cell array. Each core cell stores one or more bits of data for subsequent retrieval.
Commonly, adjacent the core is the periphery. One function of the periphery is to aid in correct circuitry selection for a certain memory location.
Charge is commonly stored in a separate polysilicon layer that is insulated both above and below the layer. Further, in an additional storage manner, charge is stored in a portion of the core generally known as the oxide-nitride-oxide (ONO) structure. Commonly, oxide functions as an insulator while nitride generally stores charge. The arrangement of the ONO structure facilitates the insulation of charge in the nitride layer by the nitride layer being sandwiched between two insulation oxide layers.
In one past method, the microchip formation process started with a silicon wafer substrate. On the silicon wafer, a bottom-most oxide layer is formed or deposited. This bottom-most oxide layer forms the bottom-most layer of the ONO structure of the core area.
The bottom and the top oxide layers of the ONO structure are formed generally in the same manner. In one manner, different gases, such as Silane, containing at least nitrogen dioxide, flow through a furnace. The silicon wafer and the oxygen from the nitrogen dioxide react to form an oxide layer. The oxide layer crystallizes on the wafer and/or the nitride layer.
The nitride layer, which is sandwiched between the two insulating oxide layers, is formed in a similar manner as the oxide layers. One way of nitride layer formation includes the use of different gases, such as Silane, containing at least silicon, hydrogen, and ammonia, flowing through a furnace. The silicon and the nitrogen from the ammonia react to form silicon nitride that crystallizes on the wafer.
While the core area typically has an ONO structure, the ONO structure is commonly etched away from the periphery area leaving only the bare silicon. A gate oxide is then commonly grown in a furnace on the bare silicon of the periphery area.
Once a gate oxide is grown on the bare periphery area, a doped polysilicon gate layer may be deposited on the gate oxide. The deposition of the polysilicon layer results in “seeds” of polysilicon formed on top of the gate oxide layer and the uppermost oxide layer of the ONO structure.
A prior method of spacer formation included blanket deposition of an oxide non-discriminately over the core and periphery of the wafer. Due to this blanket deposition, and particularly over the polysilicon line the spaces between and the area on top of the polysilicon line has a thinner deposition of oxide in comparison to the edges of the polysilicon lines. The edges of the polysilicon lines have a much thicker deposition of oxide. For example, when a blanket deposition of an oxide is deposited over polysilicon lines, approximately 1000 Angstroms of oxide fills in the space between polysilicon lines while approximately 2000 Angstroms or more of oxide fills in about the edges of the polysilicon lines. When a spacer etch is performed of approximately 1000 Angstroms, the etch will remove about 1000 Angstroms from the space between the two polysilicon lines. The spacer created at the edges of the polysilicon lines will not be entirely removed and will remain at the edge of the polysilicon lines due to a topographical effect. The height of the spacer at the edge of the polysilicon lines is due to the height (to the first degree) of the polysilicon lines. Whereas, the width of the spacer, that is, the amount it extends from the polysilicon lines into the space between two polysilicon lines, will be about ⅔ the length of the original spacer deposition. In the example immediately above of a deposition of 1000 Angstroms of an oxide, a spacer of an oxide deposition of approximately a 600 to a 650 Angstrom width extending outward and into the space located between to polysilicon lines will be formed.
In some prior methods, vertical etching was performed to form a spacer between the polysilicon lines. The etch uniformly removed oxide between the polysilicon lines and above the polysilicon lines. Yet, due to a topographical effect, the vertical spacer etch still left a thicker oxide layer at the edge of the polysilicon lines. For example, if approximately 2000 Angstroms of oxide was deposited at the edge of a polysilicon line, the spacer vertical etch would remove only approximately 1000 Angstroms of oxide while leaving approximately 1000 Angstroms of oxide at the edge. Upon deposition and prior to etch, the deposition of the oxide in the area that will form the spacer at the edge of the polysilicon lines is substantially thicker than the deposition occurring between the polysilicon lines. Little if any oxide deposition may be left between the polysilicon lines, beyond that at the edge of the polysilicon lines, after the spacer etch is performed.
The oxide spacer acts as a mask for the polysilicon line prior to the implantation step. In non-volatile memory device manufacture, it is desirable to dope the area between the polysilicon lines. Doping the silicon between the polysilicon lines forms source and drain areas. Therefore, it is generally desirable to mask or “cover” certain areas of the wafer to prevent implantation at those areas. The oxide spacer blocks the implants from being too close to the polysilicon line. It does so by “spacing” the implants from the transistor area. The etch removes the mask so implantation may occur.
Using prior methods, the non-volatile memory device core may nearly completely fill with the oxide spacer. In prior methods, the manner in which the oxide is deposited results in the polysilicon lines appearing as if they had grown together. Then, when the spacer etch is performed, hardly any exposed silicon results in the area between polysilicon lines. The presence of the oxide covering the area between the two polysilicon lines makes implantation more difficult. Therefore, by some of the prior methods, implantation in the area between the polysilicon lines had to occur before core spacer formation.